M. Amimul Ihsan Electrical and RF Engineer

M. Amimul Ihsan

Menu

Summary

Multiple years of Hands-on experience covering RFIC Design, RF System Design, Characterization on RF modules at RF Lab. And Digital Circuit Design and Layout with advanced EDA tools. Design for optimum area, power, and speed. Design for Robustness; EM, IR drop and Noise. Experience as a Technical Lead.

  • RF Design: Designed LNA, PA, LC Low Noise VCO. Nonlinearity aspects such as IP3, P1dB.
  • Experience in a variety of RF frequency bands. Microwave Design in GHz frequencies. Radar Systems.
  • RF Link Budget analysis using ADS for Gain, non-Linear, Noise, Harmonics.
  • RF Lab: Using Vector Network Analyzer (VNA), Spectrum Analyzer (SA), Signal Generator (SG), DMM Tested HPA, PA, LNA, Filters and U-D Converters. S21, S11, S22. Bands: VHF, UHF, L & K. -Matching Network.
  • Recent Project: Worked on Solid State Power Amplifier for Linearity, Gain, Power, Heating, etc. 
  • Familiarity with Antenna Design and issues.
 
  • Electronic Design: Designed high speed memory and other circuits for leading edge microprocessors.
  • Experience with several generations of Technology; 7nm-180nm CMOS. GF-45nm, SiGe, SOI & GaN.
  • Experience with post-silicon HW debugging and failure analysis and diagnosis of digital circuits.
  • Experience with microelectronics in extreme environments (high/low temperature and etc.).
  • Extensively used Advanced EDA tools (Cadence, Synopsys, etc.): DRC/LVS/EM/NOISE/IR drop.
 

Leadership skills.

A) Trained and guided Junior Electronic Engineers in high tech.

B) Experience with the initial concept to successful product. Led team in the Lab.

C) Wrote proposals for funding on research projects.

D) Presented developments and reviews to Internal and External technical audience.

Excellent communication and documentation skills with technical presentation experience.
Stanford University, CA. Electrical Engineering.

Experience

Consulting Engineer: Electronic and RF Design and Test:                                         Present 

Design Overview of Solid-State Power Amplifier (SSPA) and Multiport Transceiver Systems for Boeing Space. Proposed techniques to mitigate challenges such as Linearity, Gain, SSPA CLASSES, Power Consumption, AM-PM Conversion and etc. Tools: DOORS, APDP (WindChill).

Northrop Grumman:                                                                                                                            05/2020-2022

Lead RF System Staff Engineer:

  • Matching LNAs and PAs using VNA, SA, SG for Gain and optimizing S parameters for Transceivers.
  • Conducted research to acquire the best Wireless Access Point and RF-Coupler. P1dB and IP3.
  • Contributed on ICA (Intra Flight Data Link Control Module), Top level and Sub-Assembly MRE.
  • Tested multiple PA (Power Amplifier), Synthesizers and Up-Down Converters) with Functionalities.
  • Built and tested MADL (Multifunction Advanced Data Link) Electronics. LabVIEW programming.
  • Worked on Telemetry and RF Communication Architecture for Optical Network.
  • Proposed secondary and tertiary communication for DWDM. Some Agile/Scrum and JIRA.
 

Lockheed Martin Space Company. Sr. Staff RF Engineer:                                                               12/2018-02/2020

  • RFIC Design: LNA, PA and Mixer. Used extensively Cadence RF-Spectre Simulator. Simulated Nonlinearity aspects
    such as IP3, P1dB.     Worked on Integrated Circuit Design. Wrote MATLAB codes for GPS III Satellite.
  • Heterogeneous Package: RF Link Budget Analysis on Gain, Non-Linear, Noise, Harmonics; with ADS.
  • Contributed to the GaN process developed at Lockheed.
  • Filed invention disclosure: 1) Fixing LNA Gain Loss on board 2) Enhanced Power Amplifier. 

You may click here to view them.

IBM Microprocessor Design Team. Senior Design Engineer:                                 2018 and 2004-2006 

  • Worked with silicon debugging team on the level 1 caches diagnosing circuit and timing related hardware issues. Held design reviews on I and D-Caches. Functional Verification using ESP-CV, Verity, VGEN and ACES in different macros. Circuit design in Cadence environment.
  • Worked on the RISK Microprocessor for the Nintendo Wii chip that was widely successful.
  • Designed and implemented in engineering UNIX/LINUX workstations, Cadence’s Virtuoso tool and IBM’s internal tools such as Power Spice, Erie extraction, Niagra DRC, LVS, TLT and functional verification tool Verity. SOI integrated circuits containing complex Digital circuits. Static timing analyzer tool to analyze setup/hold time violations. Optimized WL of I and D Cache.
  • ASIC Design: Analyzed Analog and Memory circuit (Cadence-Spectre) with 7nm Technology. Interpreted data, analyze results using Monte Carlo Simulation (statistical techniques).
 

RFIC Design: Designed SRAM, LNA, PA and Voltage Controlled Oscillator.            20214-2017

  • Teaching Assistant: Graduate Courses. Electronic and Optical of Device and Lasers in Material Processing.
  • Research Assistant: Conducted research on how to make very low power devices for next generation devices beyond Tri Gate and FinFET.
  • Designed Low Power and High Efficient Voltage Controlled Oscillator, VCO. Analog Circuit: Designed TIA. Designed High Speed GHz SRAM.

 

Sun Microsystems (Oracle). Member of Technical Staff:                                      1998-2000 and 2006-2010 

  • Designed 64-bit dynamic shifter. Simulated the I-cache for Microprocessors.
  • Designed high speed Carry Look Ahead Static Adder for floating point unit. Wrote Verilog for Adder.
  • Modelled and Evaluated speed, functionality, feasibility of 64-bit dynamic shifter using HSPICE and state of the art CMOS technology. Characterized Power, Area, Noise, EM and IR drop on large digital circuits.
  • Verification Flow: Innologic, Verplex. STA, ATPG, Clock: NCVF, Sigem, Noise, SERF.
 

AMD & ARM. Microprocessors Digital and Memory Circuit Design:                                   

  • Designed SRAM’s core cell and its peripheral circuitries using CMOS technology. Optimized designs to meet required memory access time. Trained Junior engineers on Design Tools and Verification Jobs.
  • Designed different Memory and Datapath modules for Leading Edge Microprocessors.
  • Completed Bit cell simulations to determine the ratio of Read to Leakage current. Programmed EEPROM.
 

Software Skills, SW operating systems, Packages:

UNIX, LINUX, MS Windows/NT, OFFICE, MS PowerPoint, MAC OS, SOLARIS and Visual Studio

  • C#/C++, Java, Python, Assembly, UNIX shell, MATLAB and LabVIEW programming.

Tools:

Keysight: ADS. Cadence: Virtuoso, RF-Spectre, OrCAD, Schematics/Layout, Verilog and DRC/LVS/ERC. Synopsys: HSPICE, PathMill, Starsim, StarRC & ESPCV. Mentor Graphics DA & EDA tools. IBM Tools: Powerspice, Statistical Static Timing Analyser, GYM, SpiceJoules, DOORS, APDP (Windchill) and HFSS.

 

Education

MSEE. Stanford University, Stanford, CA.                                                                               2013    

Graduate Courses: RF Integrated Circuit Design, Advanced Analog IC, Advanced Digital IC Design, Advanced Semiconductor Device, Computer Architecture and Optical Micro-Nano Cavities.

BS Electrical Engineering: Texas, USA (Scholarship and State Public Grants).

Research

Research works at high tech industry:

RF Engineering:

I have conducted research on the Gallium nitride (GaN) Device for space application. Please click here ‘GaN’ to see research work on the Gallium nitride (GaN).

Electronic Engineering:

I carried out research and implemented low power design on some part of VLSI chips, mitigating the power consumption, consuming significant less current.

Research works at Stanford:

In today’s microprocessors failure of few or even one device can have catastrophic consequences on the entire chip. So, each device must be accompanied by relevant reliability and robustness. Furthermore, making each device as low power as possible will enable us save huge amount of energy and power consumption on the entire chip.

Here at Stanford, under Professor James Harris, I have conducted research on highly efficient next generation High Hole Mobility Transistor (HHMT) a key device for CMOS. Ge on Insulator (GOI) devices and their impact on performance in building next generation new devices would enable an entirely new class of hi-speed, low power, robust devices for chips and microprocessors.

I conducted research on how to create a highly efficient next generation solar cell accompanied by low-power and low-cost features. This device is based upon high absorption that would enable an entirely new class of high absorption, low-power, low cost and robust solar cells. This would allow us to take full advantage of the rapid increase in power consumption and meet the increasingly challenging demands placed on the energy supply by the demands of daily lives.

I contributed to research in other areas, including Optical Micro- and Nano-Cavities, photonic crystal cavities, plasmonic cavities, fabrication techniques. I also looked at applications of such optical cavities, including low-threshold lasers and verified these concepts through MATLAB simulation.

Project

  • Designed, tested and verified High End Microprocessors before shipping to the market.
  • Designed RF modules such as Power Amplifier, Low Noise Amplifier for Space application.
  • Designed High Efficient Voltage Controlled Oscillator, VCO with low power & cost and low phase noise
  • Designed and Simulated better SRAM array with the Minimize power consumption, Increase robustness and reduce susceptibility to process variations while maintaining high clock speed
  • Designed and optimized Fully Differential Optical Sensor Circuits.
  • Project doing research on how to make very low power devices and proposed a next generation device mitigating the current issues with deep sub-micron CMOS process.
  • Designed Wideband Transimpedance Amplifier with higher Bandwidth