Experience in Electronic Design. One of the challenges I faced while in up design teams was high power consumption by some of the memory circuits which were million times used in those CPUs. I redesigned and made a number of improvements in VLSI memory design with lower power designs. At Oracle, I designed and implemented Memory blocks, 64-bit dynamic shifter and 64-bit adder for floating point and graphics units (FGU). I published a paper on my new memory cell which was used thousands of times thus reducing the power consumption by almost 50X.

In high-tech, I have designed circuit high speed and at the same time with low power; this requires an in-depth knowledge as well as experience in low power circuit design. I have presented my professional work both in academia and industry to include Stanford and IBM, Oracle, Northrop. I have designed, verified and implemented low power circuits for RISC microprocessors (um) which were widely successful.

• You may also view some of the designs and testing of circuits/blocks for RISC Out-of-Order execution Power Architecture microprocessors that was widely successful. Here is the link of our chip. The IBM chip for the Nintendo Wii is one example.